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FRANKEN-SoC

Three compute brains on one chip, awake only when needed

A RISC-V heterogeneous SoC for event-driven AI at the edge

November 20251 contributor
RISC-VEdge AINeuromorphicSoC
FRANKEN-SoC heterogeneous die layout
96.5%
Arrhythmia detection
46k
MACs per inference
3
Compute paradigms
RV64GC
RISC-V ISA

FRANKEN-SoC

A RISC-V heterogeneous System-on-Chip that fuses a Gemmini-style dense accelerator, a lightweight vector/SIMD unit, and a neuromorphic gating tile to do the right compute at the right time, for event-driven AI at the edge.

Architecture

FRANKEN-SoC combines three compute paradigms on a single die:

  1. Dense Accelerator — Gemmini-style systolic array for matrix-heavy inference workloads
  2. Vector/SIMD Unit — Lightweight vector processing for signal conditioning and feature extraction
  3. Neuromorphic Gating Tile — Event-driven activation that routes compute only when needed, cutting idle power

The gating tile watches incoming sensor data and activates only the compute paths required for the current inference task. Dense CNN layers run on the systolic array. Lightweight preprocessing runs on the vector unit. The neuromorphic tile decides which path fires and when.

Target Applications

  • Wearable biomedical monitors (ECG, EEG anomaly detection)
  • Always-on environmental sensing
  • Edge inference for drone autonomy
  • Low-power industrial monitoring

Current Status

M0.1 milestone complete with full MIT-BIH dataset validation (86,640 windows, 48 patients). The Tiny MLP achieves 96.5% accuracy with 1.10% false negative rate at 46k MACs.